1. Field of the Invention
The present invention relates to the field of liquid crystal displays (LCDs), and more particularly, to a gate driver on array (GOA) circuit applying to LCDs.
2. Description of the Prior Art
The design of narrow bezels becomes very popular on the market. On the contrary, the border of the panel is gradually reduced. The height h of wiring layout of the GOA circuit at each stage is consistent with the size of a corresponding pixel for the conventional GOA circuit. Since products using display panels with 4 k or more pixel per inch (PPI) resolution become popular, the size of the pixel gets smaller. In other words, the room for wiring layout of the GOA circuit is decreased as well. The restriction of the height is compensated for the larger width, which is very disadvantageous to the design of the narrow bezel.
The tri-gate structure is a common method of reducing cost. With respect to tri-gate structure, the number of scan lines is triple the number of the original design while the number of data lines is one third of the original design. The use of the data lines greatly reduces. In general, a source chip, i.e. source integrated circuit (IC) is more expensive than a gate chip, i.e. gate IC, so the goal to cost saving is achieved. The use of tri-gate structure with the GOA circuit makes it possible that no gate ICs and quite a few source ICs are used in the panel. Therefore, the cost of the panel is reduced, which is quite competitive on the market.
However, the space for the GOA circuit at each stage gets smaller since the number of scan lines is triple the number of the original design after the structure of tri-gate is adopted. Based on the structure of the conventional circuit, the width of the GOA area is sacrificed, but it is not disadvantageous to the popular bezel design nowadays.
Tri-gate is often used in a low-cost panel. Take a full high definition (FHD) panel for example. A standard panel comprises 1080 gate lines and 5760 data lines. Totally, 6840 signal lines are used. A panel with tri-gate comprises 3240 common gate lines and 1920 data lines. Totally, 5160 signal lines are used. It is obvious that the panel with tri-gate has fewer signals lines than the standard panel does. No gate lines are needed for the structure tri-gate integrated with GOA. Therefore, the cost of panels is reduced to the largest scale.
The gate signal node Q(n) is a critical electric potential for the GOA circuit. When the gate signal node Q(n) is at high voltage level, the GOA circuit keeps opening and outputting. On the contrary, the GOA circuit keeps closed when the gate signal node Q(n) is at low voltage level. In the meantime, the gate signal output by the GOA circuit is also at low voltage level.
Please refer to FIG. 1. FIG. 1 is a circuit diagram of a conventional GOA circuit 10. The GOA circuit 10 comprises a plurality of GOA units 15. The plurality of GOA units 15 are connected in cascade. The GOA unit 15 at the nth stage charges a corresponding scan line G(n). The GOA unit 15 comprises a clock circuit 100, a pull-down circuit 200, a bootstrap capacitance circuit 300, a pull-up circuit 400, and a pull-down circuit 500. The basic structure of GOA unit 15 comprises the clock circuit 100, the pull-down circuit 200, the bootstrap capacitance circuit 300, and the pull-up circuit 400. The GOA unit 15 comprises four thin-film transistors (TFTs) and a capacitor. Because amorphous silicon may be unstable and unreliable, the pull-down circuit 500 is also needed except for the basic structure. The main function of the pull-down circuit 500 is to pull-down voltage of the gate line G(n), that is, to ensure that the output of the GOA circuit and the gate signal node Q(n) keep at low voltage level and that the stability of the GOA circuit in operation is enhanced.
Two auxiliary pull-down circuits are usually used in the conventional design. The function of the auxiliary pull-down circuits is pulling voltage of the gate signal node Q(n) down when the GOA circuit is closed so that the gate signal node Q(n) can keeps low voltage level. It ensures the normal working state of the panel and the increasing stability of the panel. The auxiliary pull-down circuit usually comprises more TFTs. These TFTs occupies larger space, which is disadvantageous when the narrow bezel is taken into consideration. With respect to the two auxiliary pull-down circuits, a detailed introduction is provided as follows. Please refer to FIG. 2 as well.
Please refer to FIG. 2 and FIG. 3. FIG. 2 is a circuit diagram of another conventional GOA circuit 20. FIG. 3 shows waveforms of signals applied the GOA circuit 20 as shown in FIG. 2. Compared with FIG. 1, the pull-down circuit 500 comprises a first auxiliary pull-down circuit 510 and a second auxiliary pull-down circuit 520. The first auxiliary pull-down circuit 510 and the second auxiliary pull-down circuit 520 are controlled by a low-frequency signal LC1 and a low-frequency signal LC2, respectively. The first auxiliary pull-down circuit 510 and the second auxiliary pull-down circuit 520 operate alternatively at different periods of time to ensure that the output terminal of the GOA circuit and the gate signal node Q(n) keep at low voltage level when the gate line G(n) is closed. The low-frequency signal LC1 and the low-frequency signal LC2 are inversed. When the low-frequency signal LC1 is at high voltage level, the first auxiliary pull-down circuit 510 is used to pull down the voltage of the gate line G(n) while the second auxiliary pull-down circuit 520 is at low voltage level at this time. After a plurality of frames, the low-frequency signal LC1 becomes at low voltage level and the low-frequency signal LC2 becomes at high voltage level. The second auxiliary pull-down circuit 520 is used to pull down the voltage of the gate line G(n). Further, the pull-down circuit 500 can have other structures. FIG. 3 shows that the CK signal at six stages working with the low-frequency signal LC1 and the low-frequency signal LC2 switch once about every 100 frames for producing corresponding signals of the gate line G(n). The feature of the circuit shown in FIG. 2 is that the GOA circuit at every stage corresponds to the output of a gate line G(n). Once the panel adopts tri-gate structure, the number of scan lines is triple the number of the original design while the height of space occupied by the GOA circuit at each stage becomes one third of the original design. The width of the wiring layout has to be enlarged. As a result, the border of the panel needs to be broadened, which is disadvantageous to the popular narrow bezel design.
Therefore, it is necessary to propose a GOA circuit applying to LCDs to resolve the problem happening in the conventional technology.